The present invention relates to a power converter including a power capacitor and a switching device that is composed of parallel-connected semiconductor chips and constitutes each of upper and lower arms.
FIG. 9A is a circuit diagram of a three-phase inverter that converts direct current to alternating current. The inverter has an inverter circuit 62 including six switching devices Q1, Q2, Q3, Q4, Q5 and Q6. The serially connected switching devices Q1 and Q2, Q3 and Q4, and Q5 and Q6 are connected in parallel. Diodes D1, D2, D3, D4, D5 and D6 are inversely connected in parallel to the switching devices Q1, Q2, Q3, Q4, Q5 and Q6, respectively. Each of pairs of the switching device and the diode Q1 and D1, Q3 and D3, and Q5 and D5 is referred to as an upper arm. Each of pairs of the switching device and the diode Q2 and D2, Q4 and D4, and Q6 and D6 is referred to as a lower arm.
Each of the switching devices Q1, Q3 and Q5 has a drain terminal connected to a positive input terminal 64 via a line 63, and each of the switching devices Q2, Q4 and Q6 has a source terminal connected to a negative input terminal 66 via a line 65. Plural capacitors 67 are connected in parallel between the lines 63 and 65. Each capacitor 67 has a positive terminal connected to the line 63 and a negative terminal connected to the line 65. In FIG. 9A, each of the upper and lower arms is composed of one switching device and one diode. In a case of inverter for a large amount of power, each arm is composed of plural pairs of the switching device and the diode connected in parallel, as shown in FIG. 9B.
A node Pu between the switching devices Q1 and Q2 is connected to a U-phase terminal U, a node Pv between the switching devices Q3 and Q4 is connected to a V-phase terminal V, and a node Pw between the switching devices Q5 and Q6 is connected to a W-phase terminal W. Each of the switching devices Q1, Q2, Q3, Q4, Q5 and Q6 has a gate terminal connected to signal terminals G1, G2, G3, G4, G5 and G6, and has a source terminal connected to signal terminals S1, S2, S3, S4, S5 and S6, respectively.
In a power converter, a line inductance needs to be lowered. In addition, when a switching device is composed of plural semiconductor chips connected in parallel, it is important that inductances of respective current paths from the positive terminal of the capacitor to the nodes Pu, Pv and Pw are balanced. In a power converter for a large amount of power, a bus bar is generally used for electrically connecting a capacitor to a circuit pattern on which a semiconductor chip is mounted or a circuit pattern connected to a semiconductor chip by wire bonding.
In a known power converter disclosed in Japanese Unexamined Patent Application Publication No. 2005-261035, bus bars 71 and 72, and switching devices 73 and 74 are provided, as shown in FIG. 10. The bus bar 71 is placed over the bus bar 72. The switching device 73 are arranged so as to overlap the bus bars 71 and 72 in the planar direction, while the switching devices 74 are arranged so as not to overlap the bus bars 71 and 72. Thus, imbalance and excess of peak current between the switching devices 73 and 74 is prevented. The power converter further includes plural driver circuits that operate the respective switching devices. Specifically, each of the driver circuits generates an electrical signal in response to a control signal for turning on or off the corresponding switching device, and then provides the electrical signal to a control electrode of the switching device. In the driver circuit, an impedance of a path through which the electric signal is delivered to the control electrode of the switching device 73 is designed to be larger than an impedance of a path through which the electric signal is delivered to the control electrode of the switching device 74. Alternatively, an impedance between the switching device 73 and the bus bar 71 connected by bonding wires is designed to be larger than an impedance between the switching device 74 and the bus bar 71 connected by bonding wires.
Even when each of upper and lower arms has a switching device composed of large number of semiconductor chips connected in parallel, current and voltage at the respective semiconductor chips need to be balanced. Therefore, it is suggested that the plural semiconductor chips evenly divided into two groups are mounted on different circuit patterns formed on an insulating substrate. In such a case, as schematically shown in FIG. 11, each of the upper arms has two current paths between a positive terminal PT of a capacitor and a node P that is to be connected to an output electrode (not shown). It is noted that two groups of semiconductor chips mounted on different circuit patterns are respectively represented by one switching device Q (MOSFET) in FIG. 11. To equalize the currents flowing through the two current paths, the following equation needs to be satisfied:L1+L3=L2+L4where L1 is an inductance of a current path from the positive terminal PT of the capacitor to the drain terminal of the first group of MOSFET, L2 is an inductance of a current path from the positive terminal PT to the drain terminal of the second group of MOSFET, L3 is an inductance of a current path from the source terminal of the first group of MOSFET to the node P, and L4 is an inductance of a current path from the source terminal of the second group of MOSFET to the node P.
However, when the size of the inverter is reduced, even if the bus bar is merely formed with symmetrically arranged terminal portions joined to the circuit patterns and the positive terminal PT of the capacitor is symmetrically joined to the bus bar, the inductances L1 and L2 are not equalized.
In the power converter disclosed in the reference No. 2005-261035, a mutual inductance is considered between the switching devices 73 and 74. However, the reference No. 2005-261035 does not describe that the difference of the lengths of two current paths from the positive terminal PT to the switching device Q and from the switching device Q to the node P causes the difference of the inductances of the two current paths. In a method of providing plural driver circuits, the structure of the unit becomes complicated and the unit requires an additional space for the driver circuits, resulting in enlargement of the size of the unit. In a method of using bonding wires, on the other hand, an inductance of a current path from the positive terminal of the capacitor to the switching device is considered, but an inductance of a current path from the switching device to the node for the output terminal is not considered.
The present invention is directed to providing a power converter that prevents current and voltage imbalance due to the difference of the lengths of current paths from a capacitor through plural semiconductor chips to a node that is connected to an output electrode.